UCR EE/CS 120A: Logic Design
Fall 2010
Lecture Schedule  
Lab Schedule  
Grades  
Previous course offerings  
Prereq: CS 61  
Follow-up class: EE/CS 120B  
EE/CS120A introduces you to the exciting world of digital design. Digital
circuits not only form the foundation of computers, but make possible
many of the advances around us, like cell phones, video games, medical
instruments, automotive systems, satellites, PDAs, music equipment,
military equipment, store automation. You name it -- if it runs on
electricity, it's probably got digital circuits (known as embedded
systems) inside! 120A gets you up to speed on the basics; the follow-up
course, 120B, teaches you to build a computer, and to build complete
working embedded computing systems. EE/CS 120A and 120B are taught
jointly by the EE and CS&E departments.
Catalog description :
EE/CS 120A. Logic Design (5)
Lecture, 3 hours; laboratory, 6 hours. Prerequisite(s): CS
061. Design of digital systems. Topics include Boolean algebra;
combinational and sequential logic design; design and use of
arithmetic-logic units, carry-lookahead adders, multiplexors,
decoders, comparators, multipliers, flip-flops, registers, and
simple memories; state-machine design; and basic register-transfer
level design. Laboratories involve use of hardware description
languages, synthesis tools, programmable logic, and significant
hardware prototyping. Cross-listed with CS/EE 120A
Course Objectives :
There are several specific ABET related course objetives. Please keep those objectives in mind during your study
and periodically check those objectives with your study progress.
Instructor(s) :
Dr. Sheldon Tan, Ph.D. (stan@ee.ucr.edu).
Office hours: Thursday 3:00pm-4:00am
Office:
Eng-II 424.
Lecture:
Section 001: MW 9:40am-11:00am
Sproul Hall 2339
Labs:
Section 021: MW 6:10am to 09:00pm
ENGR2 125
Labs:
Section 022: MF 2:10pm to 5:00pm
ENGR2 125
Teaching Assistants: Joe Gorden
TA office hours:
Section 021: Joe Gorden (joseph.gordon@email.ucr.edu):
Time: 2:00pm to 3:00pm (T)
in
Eng-II 109
Section 022: Joe Gorden (joseph.gordon@email.ucr.edu):
Time: 2:00pm to 3:00pm (TR)
in
Eng-II 109
Testbook:
Digital Design with RTL Design, VHDL, and Verilog, 2nd Edition
by Prof. Frank Vahid (Prof. Vahid will not receive any royalty from the sale of this text book)
Please buy the book at UCR book store (ISBN 978-0-470-53108-2)
The discounted version is also available directly from the publisher Digital Design 2nd Edition Binder Ready Version
Reference books:
Logic and Computer Design Fundamentals and Xilinx Student Edition 4.2 Package, 3/E
, by Mano and Kime, 3rd edition
Course grading:
The course consists of 100 points:
- Lecture component (65 points)
- 20 pts: Midterm
- 24 pts: Final
- 16 pts: Homeworks -- 8 @ 2 pts
- 5 pts: In-lecture exercises
- Lab component (35 points)
- 30 pts: Lab assignments
- 5 pts: In-lab practical exam(s)
Grades will be assigned using a conventional grading scale:
100-90 A, 89-80 B, 79-70 C, 69-60 D, 59-0 F. +/- grades will be given.
Students are NOT competing against one another, but rather against the
scale -- all students can get good grades if all do well.
We may adjust ("curve") an individual assessment item if such
adjusting HELPS the class.
Minimum competency requirement: We want students to master both the
conceptual as well as the hands-on aspects of the course. Thus,
students must receive a passing grade (60% or better) in each
of the lecture component and lab component, in order to receive a
passing course grade (D- or better).
Study groups:
Study groups - suggest going to the Science Library to meet and study there.
Class web site:
www.ilearn.ucr.edu
Enrolling in this course gives you automatic access to the UCR "ilearn" site
Your login id is the name field of your ucr student email address (name@student,ucr,edu),
and your initial password is your Student ID (no dashes or spaces).
Class email list:
CS/EE 120A mailing List
(send mail now or
access the
archive):
Most students will be automatically subscribed to this mailing list
when enrolled in the course. However, it is up to you to ensure that you
are in fact subscribed (you can go to the links above to check the subscription list).
Subject to change as the quarter progresses.
Read the book before lecture! Reading ahead is one of the most effective
ways of doing better in class -- you'll be amazed how much more
useful the lectures will be. We'll follow the book closely.
Also for students who can't access ilearn, please let me know so that
I can enroll you into ilearn for this course
- Week 1: Sept. 23 - Oct. 1 (Instruction begins on Sept. 23)
- T Ch1 -- Introduction, number systems (binary, decimal, hex, octal)
- T Ch2.4-2.6 -- Combinational logic circuits (gates, standard forms, Boolean algebra)
- R Ch1.1 - Ch1.3-1.4 -- Digital systems, microprocessors versus custom designs.
- Homework 1
- Week 2: Oct. 4 -- Oct. 7
- T Ch2.4-2.10 -- Combinational design(more gates, mux, decoders)
- R Ch2.1-2.3, Ch2.9-Ch2.10 -- Combinational design (design concepts, k-map, prog. logic)
- Homework 2
- Week 3: Oct. 11 -- Oct. 15
- T Ch3.2 -- Ch3.3 -- Sequential logic concept and analysis (defin, latch, flip-flop, finite stat machines)
- R Ch3.l,3.5 -- Other flip-flops (JK, T), setup and hold times, metastability.
- Homework 3
- Week 4: Oct. 18 -- Oct. 22
- T Ch3.4 -- Sequential logic design (standard design steps, D-FF based design and stat encoding)
- R Ch6.3 -- Optimization in sequential logic design (state reduction, state encoding)
- Homework 4
- Week 5: Oct.25 -- Oct. 29
- T Ch4.2 - Ch4.8, Ch5.6 Datapath components (register, shifter, counter)
- R Ch4.9 - Ch4.12 -- ALU and datapath design examples
- Homework 5
- Week 6: Nov. 1 -- Nov. 5 (Nov. 12 is Veteran Day, no missing lecture)
- R Ch6.3 - More topics in design optimization (power, timing)
- Review
- Midterm (Nov. 4)
- Week 7: Nov. 8-- Nov. 12
- T Ch4.3 Datapath components(adders, multiplier, ALU)
- Homework 6
- Week 8: Nov. 15 -- Nov. 19
- T Ch5.2 - 5.3 -- register-transfer level design, RAM design
- R Ch5.4 - 5.10 -- register-transfer level design
- Homework 7:
- Week 9: Nov. 22 -- Nov. 26 (Nov. 25-26 are Thankgiving, no lecture on Nov. 25)
- T Ch7.2 - Ch7.3 -- IC Physical Implementation and IC Design styles.
- R Ch7.4 - Ch7.5 -- Programming IC technologies.
- Homework 8
- Week 10: Nov. 29 -- Dec. 3 (Instruction ends on Dec. 3)
- Hardware Description Language -- Verilog and VHLD
- Review
Final Monday Dec. 06, 2010, 08:00am - 11:00am (same room as lecture).
Subject to change as the quarter progresses.
Read the lab overview and report format.
- Material covered: You'll be responsible for learning
material covered in lecture, in the textbook, and in lab. We expect
you to read the textbook; lecture only emphasizes key material, but
does not cover all required material alone.
- Collaboration policy
(TA/instructor may override for particular assignment):
- Midterm, final, quizzes, lab practical -- Obviously
no collaboration
- In-lecture exercises -- Dependent on instructor instructions for
particular exercise.
- Homeworks --
Collaboration strongly ENCOURAGED. Study groups are great.
You should still do your own solution, and should not turn
in *identical* solutions as others, but similar solutions
are O.K. Remember though -- these are designed to help you
on the assesment items, so relying too heavily on others will
hurt you during assessment.
- Lab assignments -- Limited collaboration may
be acceptable, but submissions must represent YOUR OWN original
work. Sharing code or team-coding are not allowed. Copying
code from ANY source (any book, current or past students, past
solutions, etc.) is not allowed. Collaboration may consist of
discussing the general approach to solving the problem, but
should not involve communicating in code or even pseudo-code.
Students may help others find bugs. Your code must be
unique -- the odds of randomly obtained highly-similar code
is very low. Design, like surgery or driving a car or
playing golf, can only be learned by doing it yourself!
- Academic dishonesty: cheating is strongly punished.
Report cheating (anonymously if you wish)
at:
https://www.cs.ucr.edu/cheating/. Note: In some courses, we use
a powerful
commercial tool that automatically compares all programs (this quarter
and from past quarters too), neglecting changes in variable names,
spacing, etc., and detects copied code. We regularly catch
several cases of copying in this course EVERY QUARTER. PLEASE,
don't risk it!!
A couple more notes. Be aware that a subset of exams may be photocopied,
for comparison with exams submitted for regrades. Also, be aware that
lying to an instructor in order to be able to make up a missed exam
or in other ways to obtain a better grade can be treated as academic
dishonesty. During exams, cell phones must be stored away in a
place not visible (e.g., inside a backpack).
- Regrade policy: regrade requests must be submitted in
writing and within one week of the distribution of the graded
material. Grade-database errors should also
be pointed out within one week of posting.
- Communicating with the instructors and TAs: when sending
electronic mail to the instructors or TAs, please remember that
many students have the same name, and your instructor may be teaching
other courses too. So please give your full name and list the
course you are referring to, and preferably include your student ID
number. We prefer that you use your UCR email account so that you
get used to it (remember that UCR sends many official notices now only
by email). Please try to be polite and professional, and use
reasonable grammar and formatting.
- Cell phones: During lectures and lab sessions, please
turn off your cell phone.
- Lab attendance: is required for the full 3-hour lab.
If you finish early, work ahead on labs, do homework, read ahead,
and help others if allowed (teaching increases your own
learning).
- Lab enrollment : To reduce disruptions and provide for the
best educational
environment, all persons in lab during scheduled lab time
should be formally registered in that section. In general, no
swapping sections and no unregistered people in the lab are allowed,
even if there are extra computers.
- Homeworks and lab reports:
Homeworks are due at the beginning of the class period on the due date.
Lab reports are due at the beginning of the lab period on the due date.
No late homeworks are accepted.
Your work must be completely typeset with a word processor.
Circuit diagrams can be drawn using any drawing program or
by hand, but it must be very neat.
Handwritten works will NOT be accepted.
Lab reports must follow this format.
- Late/early policy for lab assignments:
- Late penalty for lab assignments due before the midterm:
7% for 1-day late, 14% for 2-days, not accepted thereafter.
- Late penalty for lab assignments due after the midterm:
10% for 1-day late, 20% for 2-days, not accepted thereafter.
- BONUS for any lab assignment turned in EARLY:
2% for 1-day early, 4% for 2-days early, 6% for 3-days or more early.
- "Day early/late" is defined as 24 hours before/after the due time.
- Time Requirements: This is a five-unit engineering course.
As such,
you should expect to spend 3 hours/week in lecture, 6 hours/week in lab,
and 6 to 10 hours/week doing individual study (readings,
homeworks, programming, lab preparation, etc) -- no exaggerating here!
Please don't underestimate the time you will need to spend on this
course. These are real time amounts spent by successful past
students. Engineering and CS are challenging disciplines
requiring extensive time to master -- it's worth it in the end
(great jobs, great pay, respect, etc.), but those things don't come
for free. So practice, practice, practice! Work hard in school, then
reap the rewards of a great career.
- Final grades: Per university policy, changes to your final
grade will be made only in the event of a clerical error.
Asking your instructor how far you were from a cutoff and what
extra work you can do to improve the grade is not appropriate.