Lab 5 - 1-bit SRAM

In this lab, you will design a single bit Static Random Access Memory (SRAM) cell as shown in Figure 6-28 (page 343) of Modern VLSI Design, 3rd Edition. This lab is the first of three labs that will culminate in the design of simple Field Programmable Gate Array (FPGA). Therefore, you should work very diligently to ensure you complete this lab on-time.

Lab Procedure

The following provides the steps that you must follow to complete this lab.

1. Design and test transistor schematic for 1-bit SRAM cell.
2. Design and test layout for 1-bit SRAM cell.

Demo

You must demo the following aspects or your 1-bit SRAM design to the TA.

1. 1-bit SRAM schematic design and simulation.
2. 1-bit SRAM layout design and extracted layout simulation.

Lab Report

In addition to the standard lab report format, you must submit the following information.

1. 1-bit SRAM transistor schematic.
2. 1-bit SRAM layout.
3. 1-bit SRAM extracted layout simulation.